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mc54/74hc4051 mc74hc4052 mc54/74HC4053 analog multiplexers/ demultiplexers highperformance silicongate cmos the mc54/74hc4051, mc74hc4052 and mc54/74HC4053 utilize sili- congate cmos technology to achieve fast propagation delays, low on resistances, and low off leakage currents. these analog multiplexers/ demultiplexers control analog voltages that may vary across the complete power supply range (from v cc to v ee ). the hc4051, hc4052 and hc4053 are identical in pinout to the metalgate mc14051b, mc14052b and mc14053b. the channelselect inputs determine which one of the analog inputs/outputs is to be connected, by means of an analog switch, to the common output/input. when the enable pin is high, all analog switches are turned off. the channelselect and enable inputs are compatible with standard cmos outputs; with pullup resistors they are compatible with lsttl outputs. these devices have been designed so that the on resistance (r on ) is more linear over input voltage than r on of metalgate cmos analog switches. for multiplexers/demultiplexers with channelselect latches, see hc4351, hc4352 and hc4353. ? fast switching and propagation speeds ? low crosstalk between switches ? diode protection on all inputs/outputs ? analog power supply range (v cc v ee ) = 2.0 to 12.0 v ? digital (control) power supply range (v cc gnd) = 2.0 to 6.0 v ? improved linearity and lower on resistance than metalgate counterparts ? low noise ? in compliance with the requirements of jedec standard no. 7a ? chip complexity: hc4051 e 184 fets or 46 equivalent gates hc4052 e 168 fets or 42 equivalent gates hc4053 e 156 fets or 39 equivalent gates logic diagram mc54/74hc4051 singlepole, 8position plus common off x0 13 x1 14 x2 15 x3 12 x4 1 x5 5 x6 2 x7 4 a 11 b 10 c 9 enable 6 multiplexer/ demultiplexer x 3 analog inputs/ channel inputs pin 16 = v cc pin 7 = v ee pin 8 = gnd common output/ input 15 16 14 13 12 11 10 2 1 34567 v cc 9 8 x2 x1 x0 x3 a b c x4 x6 x x7 x5 enable v ee gnd pinout: mc54/74hc4051 (top view) outputs select l l l l h h h h x l l h h l l h h x l h l h l h l h x mc54/74hc4051 mc74hc4052 mc54/74HC4053 function table mc54/74hc4051 control inputs on channels enable select cba x0 x1 x2 x3 x4 x5 x6 x7 none l l l l l l l l h x = don't care d suffix soic package case 751b05 n suffix plastic package case 64808 1 16 1 16 j suffix ceramic package case 62010 1 16 ordering information mc54hcxxxxj mc74hcxxxxn mc74hcxxxxd mc74hcxxxxdw mc74hcxxxxdt ceramic plastic soic soic wide tssop 1 16 dt suffix tssop package case 948f01 dw suffix soic package case 751g02 1 16
mc54/74hc4051 mc74hc4052 mc54/74HC4053 logic diagram mc74hc4052 doublepole, 4position plus common off x0 12 x1 14 x2 15 x3 11 y0 1 y1 5 y2 2 y3 4 a 10 b 9 enable 6 x switch y switch x 13 analog inputs/outputs channelselect inputs pin 16 = v cc pin 7 = v ee pin 8 = gnd common outputs/inputs l l h h x l h l h x function table mc74hc4052 control inputs on channels enable select ba x0 x1 x2 x3 l l l l h x = don't care pinout: mc74hc4052 (top view) 15 16 14 13 12 11 10 2 1 34567 v cc 9 8 x2 x1 x x0 x3 a b y0 y2 y y3 y1 enable v ee gnd y 3 y0 y1 y2 y3 none logic diagram mc54/74HC4053 triple singlepole, doubleposition plus common off x0 12 x1 13 a 11 b 10 c 9 enable 6 x switch y switch x 14 analog inputs/outputs channelselect inputs pin 16 = v cc pin 7 = v ee pin 8 = gnd common outputs/inputs l l l l h h h h x l l h h l l h h x l h l h l h l h x function table mc54/74HC4053 control inputs on channels enable select cba l l l l l l l l h x = don't care pinout: mc54/74HC4053 (top view) 15 16 14 13 12 11 10 2 1 34567 v cc 9 8 y x x1 x0 a b c y1 y0 z1 z z0 enable v ee gnd z0 z0 z0 z0 z1 z1 z1 z1 y0 y0 y1 y1 y0 y0 y1 y1 x0 x1 x0 x1 x0 x1 x0 x1 none y0 2 y1 1 y 15 z0 5 z1 3 z 4 z switch note: this device allows independent control of each switch. channelselect input a controls the xswitch, input b controls the yswitch and input c controls the zswitch
mc54/74hc4051 mc74hc4052 mc54/74HC4053 ??????????????????????? ??????????????????????? maximum ratings* ??? ??? symbol ?????????????? ?????????????? parameter ?????? ?????? value ??? ??? unit ??? ? ? ? ??? v cc ?????????????? ? ???????????? ? ?????????????? positive dc supply voltage (referenced to gnd) (referenced to v ee ) ?????? ? ???? ? ?????? 0.5 to + 7.0 0.5 to + 14.0 ??? ? ? ? ??? v ??? ??? v ee ?????????????? ?????????????? negative dc supply voltage (referenced to gnd) ?????? ?????? 7.0 to + 5.0 ??? ??? v ??? ? ? ? ??? v is ?????????????? ? ???????????? ? ?????????????? analog input voltage ?????? ? ???? ? ?????? v ee 0.5 to v cc + 0.5 ??? ? ? ? ??? v ??? ??? v in ?????????????? ?????????????? digital input voltage (referenced to gnd) ?????? ?????? 0.5 to v cc + 0.5 ??? ??? v ??? ??? i ?????????????? ?????????????? dc current, into or out of any pin ?????? ?????? 25 ??? ??? ma ??? ? ? ? ??? p d ?????????????? ? ???????????? ? ?????????????? power dissipation in still air, plastic or ceramic dip2 soic package2 tssop package2 ?????? ? ???? ? ?????? 750 500 450 ??? ? ? ? ??? mw ??? ??? t stg ?????????????? ?????????????? storage temperature range ?????? ?????? 65 to + 150 ??? ??? c ??? ? ? ? ??? t l ?????????????? ? ???????????? ? ?????????????? lead temperature, 1 mm from case for 10 seconds plastic dip, soic or tssop package ceramic dip ?????? ? ???? ? ?????? 260 300 ??? ? ? ? ??? c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. 2derating e plastic dip: 10 mw/ c from 65 to 125 c ceramic dip: 10 mw/ c from 100 to 125 c soic package: 7 mw/ c from 65 to 125 c tssop package: 6.1 mw/ c from 65 to 125 c recommended operating conditions ???? ???? symbol ?????????????? ?????????????? parameter ??? ??? min ??? ??? max ??? ??? unit ???? ? ?? ? ???? v cc ?????????????? ? ???????????? ? ?????????????? positive dc supply voltage (referenced to gnd) (referenced to v ee ) ??? ? ? ? ??? 2.0 2.0 ??? ? ? ? ??? 6.0 12.0 ??? ? ? ? ??? v ???? ???? v ee ?????????????? ?????????????? negative dc supply voltage, output (referenced to gnd) ??? ??? 6.0 ??? ??? gnd ??? ??? v ???? ???? v is ?????????????? ?????????????? analog input voltage ??? ??? v ee ??? ??? v cc ??? ??? v ???? ???? v in ?????????????? ?????????????? digital input voltage (referenced to gnd) ??? ??? gnd ??? ??? v cc ??? ??? v ???? ???? v io * ?????????????? ?????????????? static or dynamic voltage across switch ??? ??? ??? ??? 1.2 ??? ??? v ???? ???? t a ?????????????? ?????????????? operating temperature range, all package types ??? ??? 55 ??? ??? + 125 ??? ??? c ???? ? ?? ? ? ?? ? ???? t r , t f ?????????????? ? ???????????? ? ? ???????????? ? ?????????????? input rise/fall time v cc = 2.0 v (channel select or enable inputs) v cc = 4.5 v v cc = 6.0 v ??? ? ? ? ? ? ? ??? 0 0 0 ??? ? ? ? ? ? ? ??? 1000 500 400 ??? ? ? ? ? ? ? ??? ns * for voltage drops across switch greater than 1.2v (switch on), excessive v cc current may be drawn; i.e., the current out of the switch may contain both v cc and switch input components. the reliability of the device will be unaffected unless the maximum ratings are exceeded. this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc54/74hc4051 mc74hc4052 mc54/74HC4053 dc characteristics e digital section (voltages referenced to gnd) v ee = gnd, except where noted v cc guaranteed limit symbol parameter condition v cc v 55 to 25 c 85 c 125 c unit v ih minimum highlevel input voltage, channelselect or enable inputs r on = per spec 2.0 4.5 6.0 1.50 3.15 4.20 1.50 3.15 4.20 1.50 3.15 4.20 v v il maximum lowlevel input voltage, channelselect or enable inputs r on = per spec 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 v i in maximum input leakage current, channelselect or enable inputs v in = v cc or gnd, v ee = 6.0 v 6.0 0.1 1.0 1.0 m a i cc maximum quiescent supply current (per package) channel select, enable and v is = v cc or gnd; v ee = gnd v io = 0 v v ee = 6.0 6.0 6.0 2 8 20 80 40 160 m a dc characteristics e analog section guaranteed limit symbol parameter condition v cc v ee 55 to 25 c 85 c 125 c unit r on maximum aono resistance v in = v il or v ih ; v is = v cc to v ee ; i s 2.0 ma (figures 1, 2) 4.5 4.5 6.0 0.0 4.5 6.0 190 120 100 240 150 125 280 170 140 w v in = v il or v ih ; v is = v cc or v ee (endpoints); i s 2.0 ma (figures 1, 2) 4.5 4.5 6.0 0.0 4.5 6.0 150 100 80 190 125 100 230 140 115 d r on maximum difference in aono resistance between any two channels in the same package v in = v il or v ih ; v is = 1/2 (v cc v ee ); i s 2.0 ma 4.5 4.5 6.0 0.0 4.5 6.0 30 12 10 35 15 12 40 18 14 w i off maximum offchannel leakage current, any one channel v in = v il or v ih ; v io = v cc v ee ; switch off (figure 3) 6.0 6.0 0.1 0.5 1.0 m a maximum offchannel hc4051 leakage current, hc4052 common channel hc4053 v in = v il or v ih ; v io = v cc v ee ; switch off (figure 4) 6.0 6.0 6.0 6.0 6.0 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 i on maximum onchannel hc4051 leakage current, hc4052 channeltochannel hc4053 v in = v il or v ih ; switchtoswitch = v cc v ee ; (figure 5) 6.0 6.0 6.0 6.0 6.0 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 m a
mc54/74hc4051 mc74hc4052 mc54/74HC4053 ac characteristics (c l = 50 pf, input t r = t f = 6 ns) v cc guaranteed limit symbol parameter v cc v 55 to 25 c 85 c 125 c unit t plh , t phl maximum propagation delay, channelselect to analog output (figure 9) 2.0 4.5 6.0 370 74 63 465 93 79 550 110 94 ns t plh , t phl maximum propagation delay, analog input to analog output (figure 10) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns t plz , t phz maximum propagation delay, enable to analog output (figure 11) 2.0 4.5 6.0 290 58 49 364 73 62 430 86 73 ns t pzl , t pzh maximum propagation delay, enable to analog output (figure 11) 2.0 4.5 6.0 345 69 59 435 87 74 515 103 87 ns c in maximum input capacitance, channelselect or enable inputs 10 10 10 pf c i/o maximum capacitance analog i/o 35 35 35 pf (all switches off) common o/i: hc4051 hc4052 hc4053 130 80 50 130 80 50 130 80 50 feedthrough 1.0 1.0 1.0 typical @ 25 c, v cc = 5.0 v, v ee = 0 v c pd power dissipation capacitance (figure 13)* hc4051 hc4052 hc4053 45 80 45 pf
mc54/74hc4051 mc74hc4052 mc54/74HC4053 additional application characteristics (gnd = 0 v) v cc v ee limit* symbol parameter condition v cc v v ee v 25 c unit bw maximum onchannel bandwidth mi i f r f in = 1mhz sine wave; adjust f in voltage to obt i 0db t v if f `51 `52 `53 mhz or minimum frequency response (figure 6) obtain 0dbm at v os ; increase f in frequency until db meter reads 3db; r l = 50 w , c l = 10pf 2.25 4.50 6.00 2.25 4.50 6.00 80 80 80 95 95 95 120 120 120 e offchannel feedthrough isolation (figure 7) f in = sine wave; adjust f in voltage to obtain 0dbm at v is f in = 10khz, r l = 600 w , c l = 50pf 2.25 4.50 6.00 2.25 4.50 6.00 50 50 50 db f in = 1.0mhz, r l = 50 w , c l = 10pf 2.25 4.50 6.00 2.25 4.50 6.00 40 40 40 e feedthrough noise. channelselect input to common i/o (figure 8) v in 1mhz square wave (t r = t f = 6ns); adjust r l at setup so that i s = 0a; enable = gnd r l = 600 w , c l = 50pf 2.25 4.50 6.00 2.25 4.50 6.00 25 105 135 mv pp r l = 10k w , c l = 10pf 2.25 4.50 6.00 2.25 4.50 6.00 35 145 190 e crosstalk between any two switches (figure 12) (test does not apply to hc4051) f in = sine wave; adjust f in voltage to obtain 0dbm at v is f in = 10khz, r l = 600 w , c l = 50pf 2.25 4.50 6.00 2.25 4.50 6.00 50 50 50 db f in = 1.0mhz, r l = 50 w , c l = 10pf 2.25 4.50 6.00 2.25 4.50 6.00 60 60 60 thd total harmonic distortion (figure 14) f in = 1khz, r l = 10k w , c l = 50pf thd = thd measured thd source v is = 4.0v pp sine wave v is = 8.0v pp sine wave v is = 11.0v pp sine wave 2.25 4.50 6.00 2.25 4.50 6.00 0.10 0.08 0.05 % * limits not tested. determined by design and verified by qualification.
mc54/74hc4051 mc74hc4052 mc54/74HC4053 figure 1a. typical on resistance, v cc v ee = 2.0 v figure 1b. typical on resistance, v cc v ee = 4.5 v figure 1c. typical on resistance, v cc v ee = 6.0 v figure 1d. typical on resistance, v cc v ee = 9.0 v figure 1e. typical on resistance, v cc v ee = 12.0 v figure 2. on resistance test setup 1.0 2.0 300 250 200 150 100 50 0 0 0.25 0.50 0.75 1.0 1.25 1.5 1.75 2.0 2.25 v is , input voltage (volts), referenced to v ee r on , on resistance (ohms) 120 100 80 60 40 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v is , input voltage (volts), referenced to v ee r on , on resistance (ohms) 120 105 90 75 60 45 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v is , input voltage (volts), referenced to v ee r on , on resistance (ohms) 90 75 60 45 30 15 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 v is , input voltage (volts), referenced to v ee r on , on resistance (ohms) 80 70 60 50 40 30 0 0 v is , input voltage (volts), referenced to v ee r on , on resistance (ohms) 25 c -55 c 125 c 25 c -55 c 125 c 30 15 5.0 5.5 6.0 25 c -55 c 125 c 25 c -55 c 125 c 20 10 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 25 c -55 c 125 c plotter mini computer programmable power supply dc analyzer v cc device under test + - analog in common out gnd v ee
mc54/74hc4051 mc74hc4052 mc54/74HC4053 figure 3. maximum off channel leakage current, any one channel, test setup figure 4. maximum off channel leakage current, common channel, test setup figure 5. maximum on channel leakage current, channel to channel, test setup figure 6. maximum on channel bandwidth, test setup figure 7. off channel feedthrough isolation, test setup figure 8. feedthrough noise, channel select to common out, test setup off off 6 7 8 16 common o/i v cc v ee v ih nc a v cc v ee v cc off off 6 7 8 16 common o/i v cc v ee v ih analog i/o v cc v ee v cc on off 6 7 8 16 common o/i v cc v ee v il v cc v ee v cc n/c a analog i/o on 6 7 8 16 v cc v ee 0.1 m f c l * f in r l db meter *includes all probe and jig capacitance off 6 7 8 16 v cc v ee 0.1 m f c l * f in r l db meter *includes all probe and jig capacitance v os v os r l v is v il or v ih channel select on/off 6 7 8 16 v cc v ee c l * r l *includes all probe and jig capacitance channel select test point common o/i 11 v cc off/on analog i/o r l r l v cc gnd v in 1 mhz t r = t f = 6 ns
mc54/74hc4051 mc74hc4052 mc54/74HC4053 figure 9a. propagation delays, channel select to analog out figure 9b. propagation delay, test setup channel select to analog out figure 10a. propagation delays, analog in to analog out figure 10b. propagation delay, test setup analog in to analog out figure 11a. propagation delays, enable to analog out figure 11b. propagation delay, test setup enable to analog out v cc gnd channel select analog out 50% t plh t phl 50% on/off 6 7 8 16 v cc c l * *includes all probe and jig capacitance channel select test point common o/i off/on analog i/o v cc v cc gnd analog in analog out 50% t plh t phl 50% on 6 7 8 16 v cc c l * *includes all probe and jig capacitance test point common o/i analog i/o on/off 6 7 8 enable v cc enable 90% 50% 10% t f t r v cc gnd analog out t pzl analog out t pzh high impedance v ol v oh high impedance 10% 90% t plz t phz 50% 50% analog i/o c l * test point 16 v cc 1k w 1 2 1 2 position 1 when testing t phz and t pzh position 2 when testing t plz and t pzl
mc54/74hc4051 mc74hc4052 mc54/74HC4053 r l figure 12. crosstalk between any two switches, test setup figure 13. power dissipation capacitance, test setup figure 14a. total harmonic distortion, test setup figure 14b. plot, harmonic distortion 0 -10 -20 -30 -40 -50 -100 1.0 2.0 3.125 frequency (khz) db -60 -70 -80 -90 fundamental frequency device source on 6 7 8 16 v ee c l * *includes all probe and jig capacitance off r l r l v is r l c l * v os f in 0.1 m f on/off 6 7 8 16 v cc channel select nc common o/i off/on analog i/o v cc a 11 v cc v ee on 6 7 8 16 v cc v ee 0.1 m f c l * f in r l to distortion meter *includes all probe and jig capacitance v os v is applications information the channel select and enable control pins should be at v cc or gnd logic levels. v cc being recognized as a logic high and gnd being recognized as a logic low. in this exam- ple: v cc = +5v = logic high gnd = 0v = logic low the maximum analog voltage swings are determined by the supply voltages v cc and v ee . the positive peak analog voltage should not exceed v cc . similarly, the negative peak analog voltage should not go below v ee . in this example, the difference between v cc and v ee is ten volts. therefore, using the configuration of figure 15, a maximum analog sig- nal of ten volts peaktopeak can be controlled. unused analog inputs/outputs may be left floating (i.e., not con- nected). however, tying unused analog inputs and outputs to v cc or gnd through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. although used here, balanced supplies are not a require- ment. the only constraints on the power supplies are that: v cc gnd = 2 to 6 volts v ee gnd = 0 to 6 volts v cc v ee = 2 to 12 volts and v ee gnd when voltage transients above v cc and/or below v ee are anticipated on the analog channels, external germanium or schottky diodes (d x ) are recommended as shown in figure 16. these diodes should be able to absorb the maximum anticipated current surges during clipping.
mc54/74hc4051 mc74hc4052 mc54/74HC4053 analog signal figure 15. application example figure 16. external germanium or schottky clipping diodes a. using pullup resistors b. using hct interface figure 17. interfacing lsttl/nmos to cmos inputs on 6 7 8 16 +5v -5v analog signal +5v -5v +5v -5v 11 10 9 to external cmos circuitry 0 to 5v digital signals on/off 7 8 16 v cc v ee v ee d x v cc d x v ee d x v cc d x analog signal on/off 6 7 8 16 +5v v ee analog signal +5v v ee +5v v ee 11 10 9 r * r r lsttl/nmos circuitry +5v * 2k r 10k analog signal on/off 6 7 8 16 +5v v ee analog signal +5v v ee +5v v ee 11 10 9 lsttl/nmos circuitry +5v hct buffer figure 18. function diagram, hc4051 13 x0 14 x1 15 x2 12 x3 1 x4 5 x5 2 x6 4 x7 3 x level shifter level shifter level shifter level shifter 11 a 10 b 9 c 6 enable
mc54/74hc4051 mc74hc4052 mc54/74HC4053 figure 20. function diagram, hc4053 figure 19. function diagram, hc4052 13 x1 12 x0 1 y1 2 y0 3 z1 5 z0 14 x level shifter level shifter level shifter level shifter 11 a 10 b 9 c 6 enable 12 x0 14 x1 15 x2 11 x3 1 y0 5 y1 2 y2 4 y3 3 y level shifter level shifter level shifter 10 a 9 b 6 enable 13 x 15 y 4 z
mc54/74hc4051 mc74hc4052 mc54/74HC4053 outline dimensions j suffix ceramic package case 62010 issue v n suffix plastic package case 64808 issue r 19.05 6.10 0.39 1.40 0.21 3.18 19.93 7.49 5.08 0.50 1.65 0.38 4.31 0 0.51 15 1.01 1.27 bsc 2.54 bsc 7.62 bsc min min max max inches millimeters dim 0.750 0.240 0.015 0.055 0.008 0.125 0.785 0.295 0.200 0.020 0.065 0.015 0.170 0.050 bsc 0.100 bsc 0.300 bsc a b c d e f g j k l m n 0 0.020 15 0.040 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dim f may narrow to 0.76 (0.030) where the lead enters the ceramic body. 18 9 16 a b c k n g e f d 16 pl t seating plane m l j 16 pl 0.25 (0.010) t a m s 0.25 (0.010) t b m s min min max max inches millimeters dim a b c d f g h j k l m s 18.80 6.35 3.69 0.39 1.02 0.21 2.80 7.50 0 0.51 19.55 6.85 4.44 0.53 1.77 0.38 3.30 7.74 10 1.01 0.740 0.250 0.145 0.015 0.040 0.008 0.110 0.295 0 0.020 0.770 0.270 0.175 0.021 0.070 0.015 0.130 0.305 10 0.040 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. 2.54 bsc 1.27 bsc 0.100 bsc 0.050 bsc a b 18 9 16 f h g d 16 pl s c t seating plane k j m l ta 0.25 (0.010) m m 0.25 (0.010) t b a m s s min min max max millimeters inches dim a b c d f g j k m p r 9.80 3.80 1.35 0.35 0.40 0.19 0.10 0 5.80 0.25 10.00 4.00 1.75 0.49 1.25 0.25 0.25 7 6.20 0.50 0.386 0.150 0.054 0.014 0.016 0.008 0.004 0 0.229 0.010 0.393 0.157 0.068 0.019 0.049 0.009 0.009 7 0.244 0.019 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 1 8 9 16 a b d 16pl k c g t seating plane r x 45 m j f p 8 pl 0.25 (0.010) b m m d suffix plastic soic package case 751b05 issue j
mc54/74hc4051 mc74hc4052 mc54/74HC4053 outline dimensions dt suffix plastic tssop package case 948f01 issue o ?? ?? ?? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. section nn seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 16x ref k n n dw suffix plastic soic package case 751g02 issue a dim min max min max inches millimeters a 10.15 10.45 0.400 0.411 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 m b m 0.010 (0.25) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b p 8x g 14x d 16x seating plane t s a m 0.010 (0.25) b s t 16 9 8 1 f j r x 45 m c k
mc54/74hc4051 mc74hc4052 mc54/74HC4053 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc74hc4051/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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